1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
Conventionally, SRAMs (Static Random Access Memories) are typically used as memory devices in certain types of electronic apparatuses such as portable phones. However, SRAMs generally have small circuit density, so that an attempt to increase memory capacity results in a significant cost increase. In contrast, DRAMs are suitable to provide a large memory capacity at low cost. In order to utilize the past assets of system configurations using SRAMs, thus, SRAM-compatible DRAMs having an interface compatible with that of SRAMs are employed.
There are several aspects in which control methods are different between DRAM and SRAM. One of such differences is a timing specification regarding an address input at the time of data write/read operation. DRAM memory cells allow only a destructive read operation by which data contents are destroyed upon access operation, so that there is a need to restore the data of sense amplifiers to the memory cells at the time of data access operation. It is prohibited to access another memory cell by changing addresses during this restore operation.
In contrast, SRAM memory cells are basically comprised of flip-flops, and thus allow a nondestructive data read operation by which data contents are not destroyed upon access operation. Accordingly, in principle, the memory cell position to which read/write access is made can be changed at desired timing by following changes in input addresses. There is a need to prevent the unintended writing of data to an unintended address, so that provision is made for an SRAM write operation such that the write operation commences as a valid access operation upon the fixing of data inputs after the retention of address inputs for a predetermined period.
In consideration of this, a DRAM designed to be compatible with the operation of an SRAM is configured such that an operation to the memory core for a read operation commences immediately after the inputting of the command, and an operation to the memory core for the write operation commences upon the end of the relevant write command cycle. Specifically, when both a chip-enable signal /CE and a write-enable signal /WE are asserted to LOW, block selection, word-line activation, and sense-amplifier activation are performed in response thereto with respect to the memory core circuit. When both the chip-enable signal /CE and the write-enable signal /WE are thereafter deasserted to HIGH, write data is fixed upon the rise edge of the write-enable signal /WE serving as a trigger, so that the write operation of specified data with respect to a specified address is performed with respect to the memory core circuit.
In the write operation as described above, there is a need for the memory core circuit to wait in the active state from the time the write-enable signal /WE is asserted to the time the write operation is performed in response to the deassertion of the write-enable signal /WE. During this period, the power supply circuit supplying a power supply voltage to the memory core circuit is also kept in the active state.
In DRAMs, generally, a stepped-up voltage Vpp, a stepped-down voltage Vii, and so on are generated form the external power supply voltage Vdd, and are supplied to the memory core circuit. The stepped-up voltage Vpp is used to drive word lines, and the stepped-down voltage Vii are used as the power supply voltage of the memory core circuit. In order to generate the stepped-up voltage and stepped-down voltage, power supply circuits such as a stepped-up voltage generating circuit and a stepped-down voltage generating circuit are used.
The stepped-up voltage generating circuit includes a detection circuit and a pump circuit. Upon the detection of a drop of the stepped-up voltage by the detection circuit, the pump circuit starts driving to boost the stepped-up voltage. The detection circuit uses a differential amplifier to detect a difference between a reference voltage Vref and a voltage made by dividing the stepped-up voltage Vpp, and supplies the outcome of the detection to the pump circuit. When the stepped-up voltage Vpp drops, the voltage made by dividing the stepped-up voltage Vpp becomes smaller than the reference voltage Vref. In response, the pump circuit starts driving to boost the stepped-up voltage Vpp.
A bias current flowing through the differential amplifier is set to an appropriate current amount in response to whether the memory core circuit is in the active state or in the inactive state. The operation speed of the differential amplifier is fast when the bias current is large. In this case, thus, it is possible to perform proper potential detection by following a sudden change in the stepped-up voltage Vpp. Accordingly, the bias current is increased to sufficiently increase the response speed of the power supply circuit when the memory core circuit is in the active state. When the memory core circuit is in the inactive state, on the other hand, the bias current is decreased to reduce needless current consumption.
Alternatively, provision may be made such that two detectors (differential amplifiers) having different response speeds and different current consumption levels are provided. The detector having faster response speed and larger current consumption is used to sufficiently increase the response speed of the power supply circuit when the memory core circuit is in the active state. When the memory core circuit is in the inactive state, on the other hand, the detector having slower response speed and smaller current consumption is used to reduce needless current consumption.
As previously described, in the write operation of an SRAM-compatible DRAM, the power supply circuit supplying a power supply voltage to the memory core circuit is placed in the active state from the time the write-enable signal /WE is asserted to the time the write operation is performed in response to the deassertion of the write-enable signal /WE. Namely, the power supply circuit supplying a power supply voltage to the memory core circuit is placed in the active state during a wait period in which a write operation is not performed with respect to the memory cells of the memory core circuit, thereby resulting in the consumption of needless electric currents. The power supply circuit continues to consume an electric current for a long period until a write operation actually commences even when the command cycle is a long cycle so that the period from the assertion of the write-enable signal /WE to the deassertion thereof is relatively long.
[Patent Document 1] Japanese Patent Application Publication No. 07-105682
Accordingly, there is a need for a semiconductor memory device that can reduce current consumption in its power supply circuit during a period in which the memory core circuit is waiting in the active state for the start of a data write operation.